D-FlipFlop - D-FlipFlop Positive Edge Triggered
Connection Diagram:
| C |
| Q |
| D | QN | |
| Connections(4) | Position | Remark |
| QN | Right | Inverted Output |
| Q | Right | Output |
| D | Left | Data |
| C | Left | Clock |
| Parameters(0) | Default | Remark |
| Function | The D-Flip-Flop changes state at he positive edge triggering of the clock input C. | |
| Status | Standard | |
| Export of Embedded C Code | YES | |
| Select from | Components\Library\Control\Digital\FlipFlops | |
See also
D-FlipFlopNegEdge, JK-FlipFlop, JK-FlipFlopNegEdge, JK-FlipFlopPosEdge, JK-MS-FLIPFLOP, SR-MS-FlipFlop, T-FlipFlop,